The invention relates to a circuit provided with a plurality of clock modules, each of which includes
a clock input for an own clock signal, PA1 a clock output, PA1 a selection input for receiving a selection signal, each clock module being switchable, under the influence of the selection signal, between a selection state and a deselection state, in which states the own clock signal is passed to the clock output and not passed to the clock output, respectively, the clock module awaiting, after deselection by the selection signal, the completion of a period of the own clock signal before switching to the deselection state and the clock module switching to the selection state, after selection by the selection signal, only after a beginning of a period of the own clock signal, provided that a condition that all other clock modules be in the deselection state has been satisfied.
A circuit of this kind is known from a publication in IBM Technical Disclosure Bulletin Vol. 32 No. 9B (February 1990), pp. 82 to 84. This publication discloses a circuit comprising two clock modules. This circuit ensures that no glitches occur upon switching over from a state in which the own clock signal of one clock module is conducted to the state in which the own clock signal of the other clock module is conducted. The circuit conducts no more than one of the own clock signals at a time to the clock output. This is achieved in that each relevant clock module prevents the other clock module from entering the selection state if the relevant clock module itself is still in the selection state.
Each of the two clock modules includes a D flipflop whose state indicates whether the relevant clock module is in the selection state or in the deselection state. In order to prevent the clock modules from simultaneously passing their own clock signal, the data loaded into the D flipflop of one clock module is filtered in dependence on the state of the D flipflop in the other clock module and vice versa. For as long as the D flipflop of the one clock module indicates the selection state, only data indicating the deselection state can be loaded into the D flipflop of the other clock module. It is only when the D flipflop in the one clock module indicates that the one clock module is in the deselection state that the selection signal can be loaded into the D flipflop of the other clock module. This takes place in response to the rising edge of the own clock signal of the other clock module.
The cited IBM publication provides for the switching between two incoming clock signals. However, it is also desirable that switching can take place between different numbers of incoming clock signals, so also more than two, and preferably at a comparatively large number of points in an integrated circuit. The design work required for this purpose should be minimized, because the design of such circuits requires great care in respect of timing.